A generic MOS latch is depicted in FIG. 1 where the latch 10 includes first and second series circuits 12 and 14 coupling first and second power supply terminals 16 and 18, in this case VDD and ground. Each series circuit includes a load 20 which could be, for example, a resistor or a current source, and NMOS transistors 22 (M1 and M2). A first terminal of the load 20 in the first series circuit is coupled to the first power supply terminal 16 and a second terminal of the load 20 is coupled to a first node 24. Similarly, a first terminal of the load 20 in the second series circuit is coupled to the first power supply terminal 16 and a second terminal of the load 20 is coupled to a second node 26. A feedback network couples the drain of one transistor to the gate of the other transistor, i.e., the gate of M1 is coupled to the second node 26 and the gate of M2 is coupled to the first node 24. The outputs, Q and Q"" are also coupled, respectively, to the first and second nodes 24 and 26.
The operation of the latch in FIG. 1 will now be briefly described. If M1 is turned ON then current flows through the first series circuit and Q is pulled low. The gate of M2 is also coupled to a low voltage and turned off. Therefore, there is no current flow and no voltage drop across the load in the second series circuit 14 so that Q"" is pulled high. This high voltage is also coupled to the gate of M1 to keep it ON. From symmetry another operating point exists for which M1 is OFF and M2 is ON.
An n-channel mosfet is said to be in triode when its gate-to-source voltage Vgs is greater than a threshold voltage Vt (this voltage is determined by the processing) and its gate-to-drain voltage Vgd is also greater than Vt. Thus, in each of the stable states of the standard bistable latch on transistor is OFF and the other is biased in triode.
An n-channel mosfet is said to be in saturation when its gate-to-source voltage Vgs is greater than Vt and its gate-to-drain voltage Vgd is less than Vt.
This circuit also possesses a third operating point, in which M1 and M2 are both biased in the saturation region and conduct equal currents. The presence of these three operating points can be verified by augmenting the circuit with voltage source Vx as shown in FIG. 2. If Vx is swept over an appropriate range, the values of Vx for which Ix=0 correspond to the FIG. 1 circuit""s operating points. An example of such a curve is shown in FIG. 3, where three operating points A, B and C are indicated. Operating point B corresponds to the third operating point mentioned above since nodes Q and Q"" are at the same potential. The FIG. 3 curve passes through operating point B with a negative slope due to the feedback structure""s loop gain being larger than unity at this operating point. For this operating point both transistors are biased in saturation. Using standard analysis methods, it is known that such an operating point must be unstable; hence, the circuit will never settle at operating point B. Therefore, the FIG. 1 circuit possesses two stable operating points.
The latch can be programmed to either stable operating point by applying an external perturbation to the outputs (e.g., by injecting differential impulse currents into Q and Qxe2x80x2) to force the latch to a desired operating point.
It has been demonstrated that an MOS latch can possess more than two stable operating points. L. B. Goldgeisser and M. M. Green entitled xe2x80x9cSOME TWO-TRANSISTOR CIRCUITS POSSESS MORE THAN THREE OPERATING POINTS,xe2x80x9d Proc. Int. Symp. on Circuits and Systems, pp. 302-305, Jun. 1999. A latch with three stable operating points, i.e., a xe2x80x9ctristable latchxe2x80x9d, would be useful in logic circuits that employ three voltage levels (called xe2x80x9cternary logicxe2x80x9d) instead of two. Examples of ternary logic circuits include 3-state memory elements, 3n digital counters, a 3-state phase detector for clock/data recovery circuits, content addressable memory, and sample and hold circuits.
Practical implementations of tristable latches have so far been difficult to achieve. An MOS tristable latch that utilizes multiple power supplies is described in the above-cited article. However, the circuit disclosed there possesses multiple power supplies. The use of a resonant tunneling diode (RTD) to realize a tri-stable latch is described in the article by Huber et al. entitled xe2x80x9cAn RTD/transistor Switching Block and its Possible Application in Binary and Ternary Adders,xe2x80x9d IEEE Trans. on Electron Devices, vol. 44, no. 12, Dec. 1997, pp. 2149-53.
However, tristable latches that can be fabricated using standard industry processes and that are practical for use in digital or mixed-signal circuitry are still needed to make ternary logic circuits that are economical and practical.
According to one aspect of the invention, a tristable latch is constructed utilizing an integrated circuit processing technology that includes MOSFETs.
According to another aspect of the invention, in any standard (bistable) latch, there exists a direct connection from the gate of a first transistor to the drain of a second transistor, and vice-versa. The corresponding tri-stable topology is constructed by placing a resistive element (typically either a resistor or a diode-connected transistor) connected in series between the gate and drain of each such connection.
According to another aspect of the invention, the resistive element is a resistor.
According to another aspect of the invention, the resistive element is a diode-connected transistor.
According to another aspect of the invention, the tristable latch is used to latch one of the three states of a ternary input signal of a ternary logic device.
According to another aspect of the invention, a method for designing a tristable latch circuit includes the steps of simulating a circuit including a standard MOS latch and a feedback circuit including a biasing element and doing graphical analysis to determine the value of a characteristic of the biasing element so that the MOS latch including the biasing element has three stable operating points.
Other features and advantages will be apparent in view of the following detailed description and appended drawings.